CCIE=0, RAMRDY=0, EEERDY=0, RDCOLLIE=0, ERSAREQ=0, ERSSUSP=0
Flash Configuration Register
EEERDY | This bit is reserved and always has the value 0. 0 (0): See RAMRDY for availability of programming acceleration RAM |
RAMRDY | RAM Ready 0 (0): Programming acceleration RAM is not available 1 (1): Programming acceleration RAM is available |
PFLSH | This bit is reserved and always has the value 0. |
ERSSUSP | Erase Suspend 0 (0): No suspend requested 1 (1): Suspend the current Erase Flash Sector command execution |
ERSAREQ | Erase All Request 0 (0): No request or request complete 1 (1): Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state |
RDCOLLIE | Read Collision Error Interrupt Enable 0 (0): Read collision error interrupt disabled 1 (1): Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). |
CCIE | Command Complete Interrupt Enable 0 (0): Command complete interrupt disabled 1 (1): Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. |